The present invention relates generally to phase locked loops and more particularly to compensated phase locked loops that generate controlled output dock signals.
Phase locked loops are employed to generate clock signals which are frequency and/or phase referenced to an external input signal. Phase locked loops are used in many fields of communication and are also employed in computer applications of data synchronization from an external source. The present invention is particularly directed to phase locked loops that are programmable to create selected pixel clocks within a computer printing system.
A phase locked loop typically consists of a phase comparator, a low pass filter, and a voltage controlled oscillator ("VCO") arranged in a feedback loop circuit as depicted in FIG. 1. The phase detector compares the phase of an input signal to the phase of the output the VCO and generates an error signal which is a measure of a phase difference of the two signals. Phase locked loops are often used to provide a stable clock output Other uses include tone decoding, demodulation, frequency multiplication, frequency synthesis and regeneration of signals. By way of example, see the following publication which provides a survey of digital phase locked loop technology: "A Survey of Digital Phase-locked Loops" by W. C. Lindsey and C. M. Chie, Proceedings of IEEE, Volume 9, Number 4, page 410, April 1981.
Broadly, a phase locked loop is considered to be a kind of filter that passes signals and rejects noise. Stated differently, the primary task of the phase locked loop is typically to reproduce an original signal while removing as much noise present in that signal as possible. To reproduce the signal, the phase locked loop makes use of a local oscillator, typically a VCO having a frequency that is substantially similar to that of the input signal, SIGIN. The VCO output and incoming signal wave forms are compared with one another by a phase detector whose output indicates instantaneous phase difference, i.e. phase error. In order to suppress noise, the error is averaged over some length of time and the average is used to establish the frequency of the oscillator.
If the input signal is well behaved and stable in frequency, the VCO will need little adjustment to be able to track the input signal. Any adjustment that is required is obtained by averaging over a long period of time thereby eliminating noise.
Many phase locked loops have been designed in the past, such as that shown in U.S. Pat. No. 4,930,142 by Whiting et at. entitled "Digital Phase Lock Loop" issued May 29, 1990, where a "divide by N" has been added between the VCO output and the phase detector in the feedback loop. The "divide by N" can be implemented as a counter or as a shift register with variable taps to set its length. The divider in the phase locked loop produces a pulse every N clock pulses and the phase comparater measures whether the divides pulses lead or lag the input pulses. This measure is quantized to a single bit in a digital system or a continuous waveform in an analog system indicating lead or lag and this quantized phase error is input to the filter.
With regard to the low pass filter, the complexity of the low pass filter varies depending on the amount of jitter and frequency variations expected. The output of an analog filter consists typically of a control signal in which voltage rises to increase the frequency of the VCO and declines to decrease the frequency of the VCO.
A problem with such phase locked loops is that N must be a preset constant quantity. If N were changed then the filter and the VCO would also have to change so that the frequency in the feedback loop is approximately that of the input signal, SIGIN and the filter is allowing a band-pass in the proper range. These changes usually involve changing hardware used in the circuit or manually adjusting the circuits themselves.
Some circuit designs require a variable frequency clock which is stable over a range of frequencies. The stability is gained through intricate circuit designs or by using a phase locked loop in which the discerning components, the filter and VCO, are adjusted dynamically to accommodate each new frequency. These solutions are expensive and impractical.
Therefore, it is an object of the invention to provide a phase locked loop which is dynamically programmable to create a stable clock output having a desired frequency.
It is another object of the invention to provide frequency programmability without requiring adjustments to individual components of the phase locked loop.
These and other objects of the invention are obvious and will appear hereinafter.